Voltage-controlled device, method and computer device capable of dynamically regulating voltage and effectively saving energy

ABSTRACT

The invention provides a voltage-controlled device, method and computer device capable of dynamically regulating voltage and effectively saving energy. The voltage-controlled device receives a VID from a CPU, determines a core voltage according to a load line defined therein, and supplies the core voltage to the CPU. The voltage-controlled device has a load line register set and a write logic. The load line register set has a plurality of registers, and the values of which represent the defined load line. The write logic changes the values of the registers in the load line register set according to a write signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a voltage-controlled device for a centralprocessing unit (CPU), particularly to a voltage-controlled device,method and computer device capable of dynamically regulating voltage andeffectively saving energy.

2. Description of Related Art

Under the situation that the warm-room effect is getting severely, mostcountries are devoted to working out solutions to deal with such aproblem. Among which, an effective and direct approach is to saveenergy. In the PC industry, a CPU plays an important role. The powerfuloperating ability thereof brings into progressive modernization of thescience and technology, while consumption of the power of the CPU is aconcerned object.

In the PC, the core voltage required by the CPU is determined by avoltage identification (VID) generated according to working modes of theCPU. FIG. IA is a block diagram showing how to supply a core voltage toa CPU 11 in a conventional PC. The magnitude of the core voltagerequired by the CPU 11 is not the same each time. For example, as theCPU 11 is entering a power-saving mode, the core voltage required by theCPU is lower than that in a normal operating mode. Therefore, the CPU 11will produce a VID according to the required operating voltage. In FIG.1A, after being generated by the CPU 11, the VID is output to a voltageregulator module (VRM) 12. And then, the voltage regulator module 12will determine the magnitude of the core voltage supplied to the CPU 11according to the VID.

In addition, a CPU supplier, such as Intel Co., has defined an equationnamed a load line with respect to the voltage and current of a CPU. Forexample, FIG. 11B shows a load line with the load current and the corevoltage respectively on X and Y axes of the plane. The coverage of theload line is that as the current of the CPU 11 varies, the voltageregulator module 12 has to change the corresponding voltage. Another keypoint of the load line is that as the CPU 11 is operated in a heavyload, the voltage thereof cannot be lower than a minimum voltage.Otherwise, the stability of the system cannot be assured. The previousapproach of supplying the core voltage to the CPU 11 according to theVID, such as reducing or increasing the CPU voltage to proceed withenergy-saving or to increase the performance of the CPU, cannot reachthe step of automatically adjusting the fitted CPU voltage according tothe load of the CPU, such that a user himself has to manually set areduced or increased CPU voltage. However, a normal system cannot alwaysbe in the situation of a light load or heavy load, such that it cannottake care of the CPU simultaneously for both saving energy andincreasing performance. For example, as the user wishes to increase theperformance of the system, he manually sets a over-voltage for the CPU.However, when in an idle situation, such an increased CPU voltage isuseless. As such, not only electric energy is wasted, but alsoheat-dissipating is becoming poorer.

SUMMARY OF THE INVENTION

An objective of the invention is to provide a voltage-controlled device,method and computer device capable of dynamically regulating voltage andeffectively saving energy, in which software programming is adopted todynamically change the slope and deviation of the load line, therebydeveloping a new load line to meet the criteria of the minimum voltage.

Another objective of the invention is to provide a voltage-controlleddevice, method and computer device capable of dynamically regulatingvoltage and effectively saving energy, in which it can correspond to arelatively low voltage as the CPU is in a light load situation, suchthat the whole power consuming can be reduced.

Further another objective of the invention is to provide avoltage-controlled device, method and computer device capable ofdynamically regulating voltage and effectively saving energy, in whichit can dynamically change the CPU voltage as the load of the CPU varies,thereby obtaining the best effect of energy-saving and in the meantime,bringing into the desired high performance of the CPU itself.

According to a feature of the invention, a voltage-controlled device isprovided to receive a VID generated by a CPU and to determine themagnitude of the core voltage supplied to the CPU based on a set loadline. The voltage-controlled device comprises a load line register set,having a plurality of registers, values of the plurality of registersrepresenting the defined load line; and a write logic, beingelectrically connected to the load line register set for changing thevalues of the registers in the load line register set according to awrite signal.

Another feature of the invention is to provide a computer device,comprising: a CPU; a clock generator, electrically connected to the CPU,for producing CPU clocks required by the operation of the CPU; a controlcircuit, connected to the CPU, for controlling operation modes of theCPU; a voltage-controlled device, connected to the CPU, for receiving avoltage identification (VID) generated by the CPU and determining themagnitude of a core voltage applied to the CPU based on a load linedefined therein, the voltage-controlled device comprising a load lineregister set, having a plurality of registers, values of the pluralityof registers representing the defined load line, and a write logic, usedfor changing the values of the registers in the load line register setaccording to a write signal; and a system controller, connected to thevoltage-controlled device through a bus, for issuing the write signalvia the bus, so as to allow the write logic to change the values of theregisters in the load line register set.

Further another feature of the invention is to provide a method forsupplying power, comprising: providing an original load line, the loadcurrent at the minimum voltage of the original load line being themaximum current thereof; varying a slope of the original load line toobtain a flat load line with its slope flatter than that of the originalload line; varying deviation of the flat load line to obtain apower-saving load line, wherein the varied deviation is set at theintersection of the power-saving load line and the original load line atthe maximum current; and receiving a voltage identification generated bya CPU to determine the magnitude of a core voltage applied to the CPUbased on the power-saving load line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram showing how to supply a core voltage to a CPUin a conventional PC.

FIG. 1B is a schematic diagram of a load line.

FIG. 2 is a schematic diagram of a voltage-controlled device of apreferred embodiment of the invention, capable of dynamically adjustingvoltages and effectively saving energy.

FIG. 3 is a schematic diagram of a computer device of a preferredembodiment of the invention, using a voltage-controlled device capableof dynamically adjusting voltages and effectively saving energy.

FIG. 4 is a schematic diagram showing dynamically adjusting a load lineof the invention.

FIG. 5 is a schematic diagram showing division of the load of a CPU intofour intervals of the invention.

FIG. 6 shows an example to interpret different setting for loads ofdifferent CPUs.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 2 is a schematic diagram of a voltage-controlled device of apreferred embodiment of the invention, capable of dynamically adjustingvoltages and effectively saving energy. The voltage-controlled device 22comprises a load line register set 221, a plurality of thresholdregisters 222, 223 and 224, a write logic 225 and a control logic 226,wherein the load line register set 221 has a plurality of registers 2211and each value of the plurality of registers represents a defined loadline. The write logic 225 is electrically connected respectively to theload line register set 221 and the plurality of threshold registers 222,223 and 224. The control logic 226 is electrically connected to each ofthe plurality of threshold registers 222, 223 and 224. The write logic225 writes (changes) the content of the registers in the load lineregister set 221 and the content of the threshold registers 222, 223 and224 according to a write signal of a bus 21.

FIG. 3 is a schematic diagram of a computer device of a preferredembodiment of the invention, using a voltage-controlled device capableof dynamically adjusting voltages and effectively saving energy. Thecomputer device comprises a CPU 31, a system controller 32, a clockgenerator 33, a control circuit 34 and the above-mentionedvoltage-controlled device 22. The CPU 31 is electrically connectedrespectively to the clock generator 33, the control circuit 34 and theabove-mentioned voltage-controlled device 22. The system controller 32is electrically connected to the voltage-controlled device 22.

The system controller 32 is connected to the voltage-controlled device22 through a standard bus 21. The clock generator 33 is used forproducing CPU clocks required by the operation of the CPU 31. Thecontrol circuit 34, connected to the CPU 31, is used for controllingoperation modes of the CPU 31, such as forcing the CPU to enter into anenergy-saving mode (TM mode). The voltage-controlled device 22 iscapable of detecting the load current of the CPU 31. In anotherembodiment, a detection unit (not shown in the drawing) may beconfigured to detect the load current of the CPU 31 and produce adetection result for outputting to the voltage-controlled device 22.

Please refer to FIG. 2 and FIG. 3. The voltage-controlled device 22 isprovided to receive a VID generated by the CPU 31 and to determine themagnitude of the core voltage (Vcore) supplied to the CPU 31 based on aload line dynamically set in the voltage-controlled device 22, in whichthe load line is set by the values of the registers 2211 in the loadline register set 221. In the embodiment, the initial power-on values ofthe registers 2211 in the load line register set 221 correspond to anoriginal load line defined by the CPU supplier. As shown in FIG. 4, theoriginal load line 41 of the corresponding VID has a loading currentwith the maximum current Imax when in the minimum voltage.

In a preferred embodiment of the invention, the write logic 225 of thevoltage-controlled device 22 is utilized to dynamically adjust theoriginal load line 41, thereby designing a power-saving load line 43capable of saving more power, and maintaining the inherent stability ofthe CPU 31. It is done as follows: Firstly, the system controller 32issues a write signal to the voltage-controlled device 22 via the bus 21such that the write logic 225 in the voltage-controlled device 22 isused to vary the values of the registers 2211 in the load line registerset 221 so as to change the slope of the original load line 41, therebyobtaining a flat load line 42 with its slope flatter than that of theoriginal load line 41, as shown in FIG. 4.

Secondly, the system controller 32 issues a write signal to thevoltage-controlled device 22 via the bus 21 such that the write logic225 in the voltage-controlled device 22 is used to vary the values ofthe registers 2211 in the load line register set 221 so as to change thedeviation of the flat load line 42, i.e. deviating the VID, therebyobtaining the power-saving load line 43, as shown in FIG. 5, in whichthe varied quantity of deviation is to allow the power-saving load line43 to intersect the original load line 41 at the maximum current Imax.Based on it, the voltage-controlled device 22 receives a voltageidentification (VID) generated by the CPU and determines the magnitudeof a core voltage applied to the CPU based on the power-saving load line43. Since the CPU voltage corresponding to the power-saving load line 43is lower than that set by the original load line 41. Thus, the objectiveof saving power is accomplished. In addition, since the CPU voltagecorresponding to the power-saving load line 43 is always not lower thanthe minimum voltage, the stability of the CPU 31 can be maintained.

Each of the above-mentioned threshold registers 222, 223 and 224 has apreset value or is set by the write logic 225 through a write signal onthe bus 21 issues by the system controller 32 so as to divide the loadsof the CPU 31 into different intervals. In the embodiment, three writethreshold registers 222, 223 and 224 are provided and respectively setwith a big, medium and small threshold value, i.e. TH1, TH2 and TH3(TH1>TH2>TH3), so as to divide the loads of the CPU 31 into fourintervals, i.e. R1, R2, R3 and R4 as shown in FIG. 5, in which intervalR1 refers to one with the CPU load bigger than the threshold value TH1,interval R2 refers to one with the CPU load bigger than the thresholdvalue TH2 but smaller than the threshold TH1, interval R3 refers to onewith the CPU load bigger than the threshold value TH3 but smaller thanthe threshold TH2, and interval R4 refers to one with the CPU loadsmaller than the threshold value TH3.

The voltage-controlled device 22 further compares the detected loadcurrent of the CPU 31 with the threshold values TH1, TH2 and TH3 tomonitor variation of the load of the CPU 31. As the load of the CPU 31varies to a different interval of R1, R2, R3 or R4, the control logic226 drives two signal lines OC 1 and OC 2 with their high/low variationsto represent the different four intervals. For example, OC 1 and OC 2both being in low represents that the load of the CPU 31 is in theinterval R1, OC 1 being in low and OC 2 being in high represents thatthe load of the CPU 31 is in the interval R2, OC 1 being in high and OC2 being in low represents that the load of the CPU 31 is in the intervalR3, and OC 1 and OC 2 both being in high represents that the load of theCPU 31 is in the interval R4.

Through the outputs of the signal lines OC 1 and OC 2, the existingloading condition of the CPU 31 of the computer device may be informed.The computer device may provide suitable resolution with respect tovarious, different CPU loads, such as connecting the signal lines OC 1and OC 2 to the clock generator 33 to control the frequency of thegenerated clocks, whereby, as the outputs of the signal lines OC 1 andOC 2 vary, the frequency of the CPU 31 is changed as well. Among which,OC 1 and OC 2 being both in low represents that the load of the CPU 31is higher so as to control the clock generator 33 to produce clocks ofhigher frequency. In contrary, OC 1 and OC 2 being both in highrepresents that the load of the CPU 31 is lower so as to control theclock generator 33 to produce clocks of lower frequency.

In addition, the signal lines OC 1 and OC 2 may also be connected to thecontrol circuit 34 such that the control circuit 34 may control workingmodes of the CPU 31 based on the outputs of the signal lines OC 1 and OC2. For example, as the control circuit 34 detects the outputs of thesignal lines OC 1 and OC 2 representing that the CPU 31 is in a lighterload, pin PROCHOT # of the CPU 31 is triggered to enable the CPU 31 toenter into a power-saving mode.

Furthermore, the signal lines OC 1 and OC 2 may also be connected to thesystem controller 32 such that based on the high or low load of the CPUrepresented by the outputs of the signal lines OC 1 and OC 2, the systemcontroller 32 may issue a write signal via the bus 21 to allow the writelogic 225 to vary the values of the registers 2211 in the load lineregister set 221, thereby changing the slope and deviation of the loadline and providing a suitable CPU voltage under different loadingconditions.

The control logic 226 of the voltage-controlled device 22 furtherprovides an output of a signal line ALTER #. The signal line ALTER #outputs a signal at the time when the load of the CPU 31 switches to adifferent interval. The signal line ALTER # is connected to an interruptinput of the system controller 32 so as to inform the computer device ofthe load change of the of the CPU using interruption, for example,informing software application program of the computer device byinterruption to enable a user of the computer device to know whichinterval the existing load of the CPU is in.

FIG. 6 shows an example to interpret different setting for loads ofdifferent CPU 31 such that it can save power in a lighter load conditionand obtain better performance in a heavier load condition. As shown inthe drawing, when the load of the CPU 31 is in the interval R1, thefrequency of the clocks generated by the clock generator 33 is increasedby 5%, when the load of the CPU 31 is in the interval R3, the frequencyof the clocks generated by the clock generator 33 is decreased by 5% andthe slope and deviation of the load line are altered, and when the loadof the CPU 31 is in the interval R4, the frequency of the clocksgenerated by the clock generator 33 is increased by 10% and the slopeand deviation of the load line are altered, forcing the CPU 31 into apower-saving mode.

It can be seen from the above that the invention is to provide avoltage-controlled device capable of dynamically regulating voltage andeffectively saving energy, and a computer device using the same, inwhich software programming is adopted to dynamically change the slopeand deviation of the load line, thereby developing a new load line tomeet the criteria of the minimum voltage, and, under the situation thatthe CPU is in a lighter load, it can correspond to a relatively low CPUvoltage, thereby decreasing the whole power consuming. In addition,through detecting the load current of the CPU and providing setting ofthe threshold values, accompanied by assistance of hardware andsoftware, as the load of the CPU is changed, the CPU voltage can bedynamically changed to obtain the best power-saving effect, whilebringing into the desired high performance of the CPU itself.

The above embodiments are merely exampled to interpret the invention forthe sake of convenience. The scope of what is claimed in the inventionshould be based on the appended claims, but not limited to the aboveembodiments.

1. A voltage-controlled device, used for receiving a voltageidentification (VID) generated by a central processing unit (CPU) anddetermining the magnitude of a core voltage applied to the CPU based ona load line defined therein, the voltage-controlled device comprising: aload line register set, having a plurality of registers, values of theregisters representing the defined load line; and a write logic, beingelectrically connected to the load line register set for changing thevalues of the registers in the load line register set according to awrite signal.
 2. A voltage-controlled device as claimed in claim 1,wherein initial values of the registers in the load line register setcorrespond to an original load line and the load current at the minimumvoltage of the original load line is the maximum current thereof.
 3. Avoltage-controlled device as claimed in claim 2, wherein the write logicchanges the values of the registers in the load line register set tovary a slope of the original load line, thereby obtaining a flat loadline with its slope flatter than that of the original load line.
 4. Avoltage-controlled device as claimed in claim 3, wherein the write logicchanges the values of the registers in the load line register set tovary deviation of the flat load line, thereby obtaining a power-savingload line.
 5. A voltage-controlled device as claimed in claim 4, whereinthe varied deviation makes the Intersection of the power-saving loadline and the original load line at the maximum current.
 6. Avoltage-controlled device as claimed in claim 1, further comprising: aplurality of threshold registers, each being respectively set with athreshold value; and a control logic, used for comparing the load of thedetected CPU with threshold values so as to monitor load changes of theCPU.
 7. A voltage-controlled device as claimed in claim 6, wherein theload of the CPU is divide into different intervals by the thresholdvalues, and the control logic drives at least a first signal line forhaving a high/low change to represent a different interval as the loadof the CPU switches to the different interval.
 8. A voltage-controlleddevice as claimed in claim 7, wherein the control logic drives a secondsignal line for outputting a signal to represent a load change as theload of the CPU switches to the different interval.
 9. A computerdevice, comprising: a CPU; a clock generator, electrically connected tothe CPU, for producing CPU clocks required by the operation of the CPU;a control circuit, connected to the CPU, for controlling operation modesof the CPU; a voltage-controlled device, connected to the CPU, forreceiving a voltage identification (VID) generated by the CPU anddetermining the magnitude of a core voltage applied to the CPU based ona load line defined therein, the voltage-controlled device comprising: aload line register set, having a plurality of registers, values of theregisters representing the defined load line; a write logic, used forchanging the values of the registers in the load line register setaccording to a write signal; and a system controller, connected to thevoltage-controlled device through a bus, for issuing the write signalvia the bus, so as to allow the write logic to change the values of theregisters in the load line register set.
 10. A computer device asclaimed in claim 9, wherein initial values of the registers in the loadline register set of the voltage-controlled device correspond to anoriginal load line and the load current at the minimum voltage of theoriginal load line is the maximum current thereof.
 11. Avoltage-controlled device as claimed in claim 10, wherein the systemcontroller issues the write signal via the bus such that the write logicchanges the values of the registers in the load line register set tovary a slope of the original load line, thereby obtaining a flat loadline with its slope flatter than that of the original load line.
 12. Acomputer device as claimed in claim 11, wherein the system controllerissues the write signal via the bus such that the write logic changesthe values of the registers in the load line register set to varydeviation of the flat load line, thereby obtaining a power-saving loadline.
 13. A computer device as claimed in claim 12, wherein the varieddeviation makes at the intersection of the power-saving load line andthe original load line at the maximum current.
 14. A computer device asclaimed in claim 9, wherein the voltage-controlled device furthercomprises: a plurality of threshold registers, being respectively setwith a threshold value; and a control logic, used for comparing the loadof the detected CPU with threshold values so as to monitor load changesof the CPU.
 15. A computer device as claimed in claim 14, wherein theload of the CPU is divide into different intervals by the thresholdvalues, and the control logic drives at least a first signal line forhaving a high/low change to represent a different interval as the loadof the CPU switches to the different interval.
 16. A computer device asclaimed in claim 15, wherein the at least a first signal line isconnected to the clock generator to drive the clock generator forcontrolling the frequency of the produced clocks.
 17. A computer deviceas claimed in claim 15, wherein the at least a first signal line isconnected to the control circuit to drive the control circuit forcontrolling working modes of the CPU.
 18. A computer device as claimedin claim 15, wherein the at least a first signal line is connected tothe system controller to drive the system controller to vary the valuesof the registers in the load line register set through the write logic.19. A computer device as claimed in claim 15, wherein the control logicdrives a second signal line, connected to an interrupt input of thesystem controller, for outputting a signal to notify a load change ofthe load of the CPU by interruption as the load of the CPU switches to adifferent interval.
 20. A method for supplying power, comprising:providing an original load line, the load current at the minimum voltageof the original load line being the maximum current thereof; varying aslope of the original load line to obtain a flat load line with itsslope flatter than that of the original load line; varying deviation ofthe flat load line to obtain a power-saving load line, wherein thevaried deviation makes the intersection of the power-saving load lineand the original load line at the maximum current; and receiving avoltage identification generated by a CPU to determine the magnitude ofa core voltage applied to the CPU based on the power-saving load line.